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Thread: Memory compression for data links

  1. #1 Memory compression for data links 
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    THE CHATPLACE TECHNICS




    In honor of Laplace, I'm building thisimaginary space that will be a complete screen of symbol to be readand encode by the two end computer that will transfer the images. Inthe imaginary space of 4K, there is the place for all characters ofthis planet in 20X20 format pixels, of about 20,736 completedcharacters. All the screen possibility will be encoded materiallyinto a memory read only device, that will trig the data stored intoby the call of the transfer screen number. In the case of Mars, thatshould be a 7 X 7 low dispersion laser array.



    This system is now improved, by theuse of single pixel (bit) in different screen space (memoryavailable), for the different use.


    For a memorysize of 2m, where in the case of a cellular phone, “m”should be 32, the bus width addressable memory, sothe size of the packets, will be 216bit. This fact, because the number of packets to be compare with thedata for matching them, to achieved a 32 bit number (integer:”m”),will be 216too, to maximize the bandwidth, that itself is achieved bymultiplication of those both number that are related by addition ofexponent, about the memory size



    The number ofoperation per second is given by the switching speed of thetransistorized system, built to perform that screening test.Operation per second = 232 * 25E-11 s = 0,931 Hz



    In conclusion, theimaginary bandwidth (bit/s) is equal to the bus widthaddressable(216)* Operation per second. And the real bandwidth is equal to the memorywidth(32) * (operation per second). The quotient of both, gives thefinal ratio, the CATS-RABBITS ratio, of the effective compressionrate of the communication...



    That ratio is from 1 to 186 361 forhuge device


    PARENTHESIS ON THE POWER GENERATEDBY THE CHATPLACE TECHNICS




    The list of device that follow doesn't include theCHATPLACE device, because it does not exist actually

    • SDRAM:
      • 4 G bytes / 10 ns : 1,5 W

    • EEPROM:
      • 512 k bytes / 70 ns : 0,1 W
      • 1 M bytes / 70 ns : 0,1 W
      • 1 M bytes / 200 ns : 0,05 W

    • LPDDR4:
      • 32 G bytes / 0,25 ns : 1 W N.B.: This 0,25 ns could theoretically be increase by burst data to 0,032 ns by adding a memory complex to compare with the packet within a 4096 Bus width, all that modifiable




    My approximate evaluation for thepower consumption, will include the others parts of the device, thatwill be estimated by doubling the power consumption of the memory.For a cell phone, with a factor CHATS-LAPINS of 2048X, it should beabout 2 W, for a 4 G bytes memory, remembering the reader that theratio shall be calculated with bits values...
    I must remember the reader, that thisratio is applied on the real bandwidth, so, without parallelism ofsome devices, you won't achieved any increase in effective data ratein the phone, but only reduced the cost of the transmission by 2048
    With a 5 M bytes transmission ratedevice, the cost of decreasing the rate and maintaining the totalphone data rate, should be:




    • With a 32 G bytes memory unit
      • A ratio of 2048, that mean 64 CHATPLACE unit parallel
      • 64/44 of the data: 1,6X

    • With 4 X 32 G bytes memory unit
      • A ratio of 2048, that mean 256 CHATPLACE unit parallel
      • 256/40 of the data: 6,4X = 32 M bytes / second At the cost of 8 W and 4 mm X (10 X 10) mm, that will be restore to the phone by lowering the WiFi bandwidth by 320X, even more

    • With a 32 G bytes memory unit
      • A ratio of 1092, 256 parallel
      • 256/21: 12,2X, but this time 160X on the WiFi, and 2 W, and 1 mm X (10 X 10) mm




    SOME ELECTRONICS




    To achieved better efficiency, thereare some designs specifications to be described:




    • The two different Bus of the single chip IC, that will included memory, are as usual address and data bus.
    • Since that scanning comparison procedure will be incremented one by one in the same way every time.
    • There is no need to input the addresses, but only to trigger the process, for synchronization purpose.
    • The total memory size of the chip IC, will be (2m/2 + 2) * (2m/2) bits. For storing the compared data packet.
    • That storage capacity is justify, by the use of very huge internal Bus width, for speed (overall time).
    • The comparison could be achieved by multi “Equal” transistorized parallel system, for # of cycles too.
    • Multi signal (cables or frequency) merge inside a separate chip IC (or the same one: heat consideration)




    The final cycle time (toproduced a “m” width “integer”) : Max ( 0,25 ns X 2m/2X 2m/2/ Internal Bus Width, 2m/2 (frommore than one signal) /achievableinput data Bus width (physical chip width) / 100 sub memory packets(0,002 ns transistor switching time, on a pin synchronization, withinthe physical input data Bus: theoretical) )



    The maximum theoretical input: 5X 100G bit/s input, but we won't achieved that The device looks to belimited only by the comparison process...



    At the end: 0,25 ns X 2m/2seconds per cycle, with an internalBus width of 2m/2= 61 kHz per parallel device



    With the 100 G bits/s cable: 51,230devices in parallel, to saturate it... with an astonishing 1,64E15bytes of memory


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  3. #2  
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    It's awesome theory. It reminds me a little an institutional-grade alternative investment fund that seeks to capture alpha from uncharted parameters in digital assets. By way of volatility harvesting and decorrelating algorithms, the firm identifies market dislocations that drive risk-adjusted investment opportunities


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  4. #3  
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    Quote Originally Posted by mariopepper View Post
    It's awesome theory. It reminds me a little an institutional-grade alternative investment fund that seeks to capture alpha from uncharted parameters in digital assets. By way of volatility harvesting and decorrelating algorithms, the firm identifies market dislocations that drive risk-adjusted investment opportunities
    ??? You must be a bot.
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  5. #4  
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    Quote Originally Posted by mariopepper View Post
    It's awesome theory. It reminds me a little an institutional-grade alternative investment fund that seeks to capture alpha from uncharted parameters in digital assets. By way of volatility harvesting and decorrelating algorithms, the firm identifies market dislocations that drive risk-adjusted investment opportunities
    Truly awesome, yea. Yea, verily, yea. In deferred sectors, always restructure non-defaulted short positions. Re: Revolving liability structures: in the financial sector, be sure to amortize thrice daily. The smart investor this season will never leverage pooled securities, but will secure pool levers in Liverpool. The smart trader nowadays will plan to securitize counterparty debt tranches. Banana banana, sis boom bah, toward a transformative hermeneutics of quantum gravity.
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  6. #5  
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    Quote Originally Posted by mariopepper View Post
    It's awesome theory. It reminds me a little an institutional-grade alternative investment fund that seeks to capture alpha from uncharted parameters in digital assets. By way of volatility harvesting and decorrelating algorithms, the firm identifies market dislocations that drive risk-adjusted investment opportunities
    To be fair, this does make a lot more sense than the OP.
    ei incumbit probatio qui dicit, non qui negat
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